1. Background

In recent decades, with the development of micro -electronic technology, high -performance, small, and low -cost electronic products have become the basic demand for the market. The number of components can be accommodated on the integrated circuit that meets the prediction of Moore's law. However, in recent years, the growth trend of traditional integrated circuits has begun to have different models from the ideal model of Moore's law. With the rapid development of mobile phones and various electronic products, the functions of chips are becoming more and more complicated. The number of transistors on the chip is increasing, and it has also caused the increase in the volume of integrated circuits and increased power consumption. When the grid length and oxidation layer thickness of the transistor is close to the physical limit, the two -dimensional integration will eventually reach the end of the road.

The three -dimensional integration technology that follows Moore's law can be used as a solution to the above problems. The concept of the three -dimensional integration method is based on the new position of the integrated circuit: Z axis. This means that the location of the chip is no longer limited to the X-Y two-dimensional plane. Therefore, we can achieve a larger density integrated circuit stack to shorten the interconnection and reduce the visible surface, thereby reducing the size of the chip and improving the efficiency of the chip, thereby improving the application range. In addition, the three -dimensional integrated scheme can combine the optimal process of different integrated circuits itself to avoid the problem of low efficiency and low yield.

Although three -dimensional integration has many advantages, its material selection, the physical design and testing methods of thermal drive are the current problems to be solved. This article summarizes the wafer -grade three -dimensional integrated circuit technology. In three -dimensional integration technology, the popular and highly reliable popular technology is silicon -based perforation technology. In the following narrative, this key technology will also be introduced. At the same time, several different types of wafers and stacking methods, as well as challenges such as test methods, reliability, material selection such as 3D integration. This information will provide guidelines and reference for researchers interested in this area.

2. The key technologies for wafer -level 3D integration

The wafer -level three -dimensional integration is a new concept that uses many advanced technologies to increase the increase in circuit density and the size of the volume. In this article, the three most important technologies are introduced.

2.1 Apity and key combination

Poor circuit failure or reliability in uncertainty. Therefore, the yield of the chip contact area and the three -dimensional integrated circuit stacked by the high and low of the accuracy. The accuracy of the alignment is related to the alignment marker. It is also affected by the personal experience of the operator.

Copper is widely used in standard CMOS manufacturing. Therefore, copper is the best choice to connect two device layers or wafers in three -dimensional integration. The principle of the copper wafer bond is to make two chips contact and then heat up. During the key combination, the copper layer of the two chips can diffuse from each other to complete the key combination process. The integration quality is related to the cleanliness and bonding time of the wafer surface.

Generally speaking, the temperature can be completed at least 300 to 400 ° C. You can determine the key quality according to the form of the interface. In order to obtain the results of the combined copper chip bond, the condition is heated for 30 minutes at 400 ° C, and then annealing at 400 ° C nitrogen environment for 30 or 60 minutes. Although high temperature and high voltage may improve the quality of the bonding, the corresponding cost and the loss of equipment have also become the main problems that need to be concerned. Therefore, the key combination method at lower temperature and pressure is the main purpose of three -dimensional integration.

2.2 Wall thinning technology

The three -dimensional integration technology has greatly increased the density of integrated circuit and also brings the problem of heat dissipation difficulties. Due to the resistance between the silicon -based plate and the metal material, when the current is passed, there will be a thermal effect. The constant heat generation will cause a internal stress on the back of the chip, and when the internal stress is large, it will directly rupture the chip and speed up the damage speed of the chip. By using the chip thinning process, not only can effectively reduce the internal resistance of integrated circuits, optimize the heat dissipation performance of each chip, but also improve the stability of the circuit and reduce the chip volume, and it is more in line with the trend of the overall miniaturization of the integrated circuit.

2.3 Silicon -based Plate Passage Technology (TSV)

Silicon -based perforations (TSV) Make vertical pupils between chips and chips, between wafers and wafers to achieve the technology of interconnection between chips. This technology can maximize the density of the chip stacking in the three -dimensional direction. Therefore, after the chip of different substrates is integrated with a three -dimensional stack through the perforation technology of the silicon -based plate, it can not only shorten the metal wire and connected resistance, but also reduce the size of the chip.

(1) First through the holes. The first -hole technology is to complete the pore production and the filling of the conductive material on the blank silicon wafer before the CMOS device is made. In this scheme, filling materials cannot be metal, such as copper. In addition, since there is no metal interconnection at this stage, the longitudinal width ratio of the hole process is less than the rear hole process.

(2) Lacofori process. After the Beol is completed, the CMOS is about to be completed and the silicon wafer that is about to be completed and but has not yet been thinned. This technology includes drilling and filling process. In order not to damage equipment and circuits, it should be produced at a temperature environment lower than the thermal budget.

(3) TSV process process. The perforation of the entire silicon -based plate can be roughly divided into two parts: the first part is the etching of the hole, and the second part is filled with the hole. The erosion of the perforation of the silicon -based plate depends on the thickness of the wafers after thinning. When the target etching depth is too deep, the opening size of the pores needs to be expanded accordingly, which also leads to an increase in chip size. Filling materials are also a problem that needs to be considered. Copper, tungsten, and polysilicon are typical silicon -based plate perforation filling materials. Among these materials, copper and tungsten can only be used in the rear hole scheme, and polysilicon can be used in the pores and the rear hole scheme.

Copper is a compatible material, with fewer residual stress and good electronic performance, but it is difficult to fill the high -vertical width ratio. On the contrary, tungsten is easy to fill the high -width ratio, but its residual stress is a big problem. Polycrystalline silicon can be used in the athletic scheme of the perforation of the silicon -based plate, but its resistance is higher than the metal. Considering the advantages and disadvantages of each material, the choice of silicon -based plate perforated filling materials is of great significance for three -dimensional integration, especially for wafer -level three -dimensional integration.

TSV preparation specific process steps are:

(1) Thin the chip through the grinding and etching process.

(2) Plugs on the chip through the laser melting method or reflecting the ion etching method.

(3) Use the plasma chemical chemical gas sedimentation method (PECVD) to create the insulation layer on the side wall of the hole.

(4) Remove the substrate oxidation layer at the bottom of the hole to expose the metal layer.

(5) Fill the copper metal into the hole in the pores.

(6) Remove the copper metal on the surface of the chip through chemical machinery grinding and etching.

3. Classification of wafers

(1) Silicon. Body silicon is the most commonly used wafer material in wafer -grade three -dimensional integration. The reason is not only at its cost, but also a mature production process. Even when other types of chips are used as top chips, the bottom chip is usually a silicon chip.

(2) Insulation silicon (SOI). The surface of the SOI chip has a covered oxidation layer that can be uniformly reduced, because the oxidation layer plays a role in hindering etching. The etching process can use mechanical grinding, wet etching, and dry etching. The most important thing is that the final thickness can be evenly reduced, and the use of SOI can achieve high -density three -dimensional integration. The SOI structure can effectively avoid the phenomenon of locking. However, the anti -static capacity of stacking structures may be reduced, and dense equipment layers also have potential heat dissipation problems.

(3) Glass. Glass wafer in 3D integration is usually used to place top chips. Therefore, glass wafers used for this purpose are called carrier wafers. When the glass is temporarily attached to the top wafers, you can reduce the substrate of the top wafer. After the thin wafer bond is closed at the bottom of the wafer, remove the glass. The transparent characteristics of glass wafers also helps the results of good key combination. For various types of wafer stacks, we should notice that if any charger is exposed or the wafer is close to the wafer, the wafer may generate inductive charge. In the stacking process of two wafers, as long as a chip is charged, the electrostatic discharge event may occur.

4. Walls and stacking methods

According to the stacking direction of the two chips, it is divided into two different stack chips: face -to -face and face. The impact of the chip stacking direction is very huge, which will affect the symmetry of the circuit, the difficulty of manufacturing, and the interconnection of the capacitance. Both stacking methods have been applied to three -dimensional integrated applications. Even the common use of the two stack methods exists.

(1) Facial stacking method. For these types of chips, the metal layer (facial) of the two chips is connected in the circuit through TSV. From the perspective of manufacturing technology, this integration method is easy to invest and does not require additional processing chips. But it is necessary to consider the symmetry of wafers to wafers. This means that when designing the top chip, the circuit needs to perform mirror operation. At the same time, we must also consider the symmetry and confrontation of the two chips.

(2) Facing the back stacking method. Facing the back wafer, the metal layer (face) of a chip is connected to the substrate (back) of another chip through the TSV, and the wafer (wafer or top wafer) should be thinned. Compared with the face type, this method increases the complexity of the process. However, the symmetry of wafer to wafers does not exist. And the chip that needs to be processed is obvious, and the wafer is thin enough, and the calibration process becomes much easier.

It can be seen from the above introduction that the first -hole technology and the back -passing process have their own characteristics. Therefore, in the process of integration of the actual circuit, the stacking method should be reasonably selected according to different needs.

5. The advantages and challenges of wafer -level 3D integration

Different from the traditional two -dimensional packaging technology, the wafer -level three -dimensional integration provides more advantages, including:

(1) Multiple different devices connect to each other in the vertical direction, shorten the interconnection, and reduce the visible surface, thereby narrowing the size of the chip and increasing the integrated density.

(2) The shortening of connection between the chips has accelerated the speed of chip processing.

(3) Low power consumption and higher operating speed brought by low -resistance.

(4) The overall size is small, reducing the integrated cost. However, the challenges such as cooling problems, alignment methods, materials selection, and three -dimensional design CAD tools, design and testing methods brought by high integration density still need to overcome.

6. Conclusion

Due to the restrictions of traditional methods, industry cannot integrate many circuits as much as before. Three -dimensional integration technology provides a new version of the new version that can continue Moore's law. The TSV interconnection technology in 3D integration can directly connect the chip in the vertical direction, which greatly improves the integrated density and reduces the size of the integrated circuit. However, three -dimensional integration also faces many technical challenges, such as material selection, heat dissipation problems and testing methods. With the efforts of the industrial and academic circles, three -dimensional integrated technologies with small advantages such as small appearance, high density, and low cost, have very broad application prospects in high -performance and low -power next -generation integrated circuit revolution.

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